In a display device such as, for example, an active matrix type liquid crystal display device using liquid crystal cells as pixel display elements (electro-optical elements), there is known a dot sequential driving type horizontal driving circuit of a structure employing, e.g., a clock drive method. FIG. 19 shows a conventional example of such a horizontal driving circuit based on the clock drive method. In the structure of FIG. 19, the horizontal driving circuit 100 includes a shift register 101, a clock extracting switch group 102, and a sampling switch group 103.
The shift register 101 is composed of n shift stages (transfer stages) and, in response to an input horizontal start pulse HST, performs a shift operation synchronously with horizontal clock signals HCK and HCKX of mutually opposite phases. Consequently, from the respective shift stages of the shift register 101, there are sequentially outputted shift pulses Vs1 to Vsn of which pulse widths are equal to the respective periods of the horizontal clock signals HCK and HCKX, as shown in a timing chart of FIG. 20. These shift pulses Vs1 to Vsn are supplied respectively to switches 102-1 to 102-n of the clock extracting switch group 102.
The switches 102-1 to 102-n of the clock extracting switch group 102 are connected, each at one end thereof, alternately to clock lines 104-1 and 104-2, which input the horizontal clock signals HCKX and HCK respectively. In response to shift pulses Vs1 to Vsn delivered from the respective shift stages of the shift register 101, the switches 102-1 to 102-n are turned on sequentially to thereby extract the horizontal clock signals HCKX and HCK in sequence. The clock pulses thus extracted are supplied as sampling pulses Vh1 to Vhn to switches 103-1 to 103-n of the sampling switch group 103 respectively.
The switches 103-1 to 103-n of the sampling switch group 103 are connected, each at one end thereof, to a video line 105 for transmission of a video signal Video therethrough. In response to the sampling pulses Vh1 to Vhn extracted and delivered sequentially via the switches 102-1 to 102-n of the clock extracting switch group 102, the switches 103-1 to 103-n are turned on sequentially to thereby sample the video signal Video and then supplies the sampled signal to signal lines 106-1 to 106-n of a pixel array (not shown).
In the horizontal driving circuit 100 of the clock drive system in the conventional example mentioned above, the pulses are somewhat delayed due to the wiring resistance, parasitic capacitance, and so forth in the process of transmission from extraction of the horizontal clock signals HCKX and HCK via the switches 102-1 to 102-n of the clock extracting switch group 102 to delivery of such extracted signals as sampling pulses Vh1 to Vhn to the respective switches 103-1 to 103-n of the sampling switch group 103.
Such delay of the pulses caused in the process of transmission rounds the waveforms of the sampling pulses Vh1 to Vhn. Consequently, with regard to the second-stage sampling pulse Vh2 for example, there occurs a waveform overlap, as obvious particularly from a timing chart of FIG. 21, between the second-stage sampling pulse Vh2 and each of the preceding first-stage sampling pulse Vh1 and the following third-stage sampling pulse Vh3.
Generally, at the moment when each of the switches 103-1 to 103-n of the sampling switch group 103 is turned on, a charge/discharge noise is superposed on the video line 105, as shown in FIG. 21, due to the relationship of the potential to the signal lines 106-1 to 106-n. 
Under such circumstances, if there exists an overlap between the sampling pulse Vh2 and the pulse of the preceding or following stage as described, the charge/discharge noise derived from turn-on of the third-stage sampling switch 103-3 is sampled at the second-stage sampling timing based on the sampling pulse Vh2. The sampling switches 103-1 to 103-n sample and hold the potential of the video line 105 at the timing when the sampling pulses Vh1 to Vhn are turned to an “L” level.
At this time, the charge-discharge noises superposed on the video line 105 are varied, and the timings of turning the sampling pulses Vh1 to Vhn to an “L” level are also varied, so that the sample potentials obtained through the sampling switches 103-1 to 103-n are consequently varied. As a result, such variations of the sample potentials appear to be vertical streaks on the display screen to eventually deteriorate the image quality.
Meanwhile in an active matrix type liquid crystal display device of the dot sequential driving system, as the number of horizontal pixels in particular increases with advance of attaining a higher definition, it becomes difficult to ensure a sufficient sampling time to sequentially sample, in regard to the entire pixels, the input video signal Video of one route within a limited horizontal effective interval. Therefore, in order to ensure a sufficient sampling time, there is adopted a method whereby, as shown in FIG. 22, the video signal is inputted in parallel through m routes (where m is an integer greater than two), while m sampling switches are provided for m horizontal pixels as a unit, and the m pixels as a unit are written sequentially by driving the m sampling switches simultaneously in response to one sampling pulse.
There is considered now one case of displaying a thin black line of a width less than the number m of unit pixels. When such a black line is to be displayed, the video signal Video is inputted with a waveform of FIG. 23(A) wherein the black level portion thereof is shaped like a pulse, and the pulse width thereof is equal to the pulse width of the sampling pulse (B). It is ideal that this pulse-shaped video signal Video has a rectangular waveform, but due to the wiring resistance, parasitic capacitance, and so forth in the video line for transmission of the video signal Video, the leading and trailing edges of the pulse waveform are somewhat rounded (video signal Video′) as shown in FIG. 23(C).
If the pulse-shaped video signal Video′ having such rounded leading and trailing edges is sampled and held in response to the sampling pulses Vh1 to Vhn, there arises an error that, regarding the pulse-shaped video signal Video′, which is essentially to be sampled and held by the kth-stage sampling pulse Vhk, the leading edge thereof is actually sampled and held by the preceding-stage sampling pulse Vhk−1, or the trailing edge of the video signal Video′ is sampled and held by the follow-stage sampling pulse Vhk+1. As a result, a ghost is generated. Here, a ghost signifies an undesired disturbing image caused in duplicate with a deviation from the normal image.
The phase relationship of the video signal Video′ (hereinafter referred to simply as video signal Video) to the sampling pulse Vhk can be changed in six steps of, e.g., S/H=0 to 5, as shown in FIG. 24, by adjusting the sample-and-hold position on the time base of the video signal Video in a circuit, which processes the video signal Video.
Now a description will be given on the ghost occurrence dependency relative to the sample-and-hold operation. First, there is considered a state where S/H=1. FIG. 25 shows the phase relationship between the video signal Video and the sampling pulses Vhk−1, Vhk, and Vhk+1 when S/H=1 and also shows the potential changes on the signal line. When S/H=1, the pulse-shaped video signal Video is sampled and held by the sampling pulse Vhk, so that a black signal is written in the signal line of the kth stage and a black line is displayed.
However, simultaneously therewith, the black signal is written also in the signal line of the k−1th stage since the black signal portion (pulse portion) of the video signal Video overlaps with the sampling pulse Vhk−1 of the k−1th stage. Consequently, as shown in FIG. 26, a fore ghost is caused at a position of the k−1th stage, i.e., anterior in the horizontal scanning direction. Similarly, when S/H=0, the black signal portion of the video signal Video overlaps with the sampling pulse Vhk−1 of the k−1th stage, so that a fore ghost is caused at an anterior position in the horizontal scanning direction.
Next, there is considered another state where S/H=5. FIG. 27 shows the phase relationship between the video signal Video and the sampling pulses Vhk−1, Vhk, and Vhk+1 when S/H=5 and also shows the potential changes on the signal line. In the case of S/H=5, the video black signal overlaps with the sampling pulse Vhk+1 of the k+1th stage. The black signal is written in the signal line of the k+1th stage when the sampling switch is turned on, and then the potential level is lowered to return to the gray level. However, since the amount of overlap is great, the signal line potential fails to return completely down to the gray level. Therefore, as shown in FIG. 28, a back ghost is caused at a position of the k+1th stage, i.e., posterior in the horizontal scanning direction.
In any other case of S/H=1 to 4, as in the above-described case of S/H=5, the video black signal overlaps with the sampling pulse Vhk+1 of the k+1th stage, and the black signal is written in the signal line when the sampling switch is turned on. However, since the amount of overlap is smaller and the written black level is lower in comparison with the above case of S/H=5, the signal line potential returns completely down to the gray level. Consequently, no ghost is caused.
In the process mentioned, a ghost is derived from the overlap between the video signal Video and the sampling pulse. Here, the number of sample-and-hold positions, where no ghost is caused at any of anterior and posterior positions as in S/H=2, 3, 4, is defined as a margin to a ghost (hereinafter referred to as ghost margin).
Thus, it is impossible to eliminate the problem that the waveform of the pulse-shaped video signal Video are rounded at its leading and trailing edges due to the wiring resistance, parasitic capacitance, and so forth existing in the video line, but occurrence of a ghost can be avoided by properly setting an optimal sample-and-hold position in the circuit, which processes the video signal Video.
However, since the waveform of the pulse-shaped video signal Video is rounded at its leading and trailing edges by the wiring resistance, parasitic capacitance and so forth in the video line, the pulse waveform portion of the video signal Video is distorted to overlap with the sampling pulse in the preceding or following stage, so that it is rendered impossible to attain a large ghost margin correspondingly thereto. In the example mentioned above, the ghost margin is limited to three, i.e., S/H=2, 3, 4.
Next, a description will be given on a conventional active matrix type display device based on a dot sequential driving system where a clock drive method is applied to its horizontal driving circuit of a divided sample-and-hold system. The conventional active matrix type display device is composed of a panel having gate lines in rows, signal lines in columns, and pixels arrayed to form a matrix in the intersections of such rows and columns. Each of the pixels includes, e.g., a thin film transistor (TFT) as an active element. There are further provided a vertical driving circuit and a horizontal driving circuit. The vertical driving circuit is connected to each of the gate lines and selects the row of the pixels sequentially. The horizontal driving circuit is connected to each of the signal lines and writes the video signal in the pixels of the selected row. In the dot sequential driving system, the video signal is written dot-sequentially in the pixels of the selected row.
In the active matrix type display device, there exists a parasitic capacitance between a source/drain electrode of the TFT and each of the signal lines. Some image fault including vertical streaks and so forth may occur when a potential variation derived from such parasitic capacitance at the time of writing the video signal via one signal line has plunged into the adjacent signal line. This vertical streak fault becomes conspicuous particularly when a checkered pattern is displayed by a line inverse driving system. Alternatively, a vertical streak is liable to occur when a horizontal line having a thickness of one dot (one pixel) is displayed by the line inverse driving system.
In order to prevent such plunge of a video signal between signal lines, there is proposed a divided sample-and-hold driving method, which is disclosed in Japanese Patent Laid-open No. 2000-267616 for example. According to this divided sample-and-hold method, an input video signal is separated into two routes, and at the time of writing the video signal by the dot sequential system, the signals of the two routes are written while being overlapped with each other in mutually adjacent pixels.
FIG. 29 typically shows an example of a display device adopting the above divided sample-and-hold driving method. As shown in the diagram, the display device is composed of a panel having gate lines 113 in rows, signal lines 112 in columns, pixels 111 arrayed to form a matrix in the intersections of such rows and columns, and two video lines 125 and 126 for supplying video signals Video 1 and Video 2 separated into two routes in a predetermined phase relationship. Further, a sampling switch group 123 is disposed correspondingly to each signal line 112, and two signal lines are connected as a unit between the two video lines respectively. More specifically, the first signal line is connected to one video line 125 via the sampling switch, and the second signal line is connected to the other signal line 126 via the sampling switch. Thereafter, the third and subsequent signal lines are also connected alternately to the two video lines 125 and 126 via the sampling switches. The panel further includes a vertical driving circuit 116 and a horizontal driving circuit 117 provided therein. The vertical driving circuit 116 is connected to each gate line 113 and selects the rows of the pixels 111 sequentially. In other words, the pixels 111 arrayed to form a matrix are selected row by row sequentially. The horizontal driving circuit 117 operates in accordance with a clock signal of a predetermined period and sequentially generates sampling pulses A, B, C, D, . . . , which are not overlapped with respect to the switches of the sampling switch group 123 connected to the same video line but are overlapped with respect to the adjacent switches, hence turning on or off the switches in sequence to thereby write the video signal dot-sequentially in the pixels 111 of the selected row. The display device further has a clock generating circuit 189 to supply a clock signal HCK, which serves as an a reference to the operation of the horizontal driving circuit 117, and also supplies a start pulse HST. The horizontal driving circuit 117 is composed of shift registers (S/R) 121 connected in a multiplicity of stages and transfers HST in response to HCK sequentially to thereby generate the above-described sampling pulses A, B, C, D, and so forth.
Referring now to a waveform chart of FIG. 30, a brief explanation will be given on the operation of the conventional display device shown in FIG. 29. As described, the horizontal driving circuit operates in accordance with a clock signal HCK and transfers a start pulse HST sequentially to thereby generate sampling pulses A, B, C, D, and so forth. As obvious from this waveform chart, the sampling pulses overlap with each other between the mutually adjacent signal lines. That is, the sampling pulse A corresponding to the first signal line overlaps with the sampling pulse B corresponding to the second signal line. Similarly, the sampling pulse B corresponding to the second signal line overlaps with the sampling pulse C corresponding to the third signal line. Since the video signal is supplied from separate video lines to the mutually adjacent signal lines, no problem arises from such overlap. Sampling pulses are generated in such a manner as to overlap with respect to the sampling switches of the mutually adjacent signal lines, so that it becomes possible to prevent the vertical streak fault that has been known heretofore. More specifically, a parasitic capacitance is existent between the source/drain electrode of each pixel transistor and each of the signal lines, and if a potential variation on one signal line plunges into the adjacent signal line via such parasitic capacitance, no harmful effect is exerted by such plunge of the video signal as the relevant signal line is kept at a low impedance due to the overlap sampling.
In the shown example, a signal potential Sig1 is sampled and held, in response to the sampling pulse A, on the corresponding first signal line. Subsequently, a signal potential Sig2 is sampled and held, in response to the sampling pulse B, on the second signal line. At this time, a potential change is produced on the second signal line. Although this potential change plunges also into the first signal line because of the parasitic capacitance, the first signal line is kept at a low impedance since the corresponding sampling switch is still open at this time, so that no harmful effect is exerted despite such plunge of the signal.
FIG. 31 typically represents the video signal sampling timing to each signal line and the potential change produced on each video line. Fundamentally, each sampling pulse is so generated as not to overlap with respect to the sampling switches connected to the same video line. For example, the first signal line and the third signal line are connected to the same video line. Therefore, the circuit is so designed that, in principle, the sampling pulse A and the sampling pulse C do not overlap with each other. Actually, however, some delay is derived from the wiring resistance, parasitic capacitance, and so forth in the process of transmitting the pulses, hence rounding the waveform. As a result, a partial overlap is caused between the sampling pulse A and the sampling pulse C. When the sampling pulse C rises in such a state, the corresponding sampling switch is opened and a charge/discharge is generated to the signal line, whereby a potential fluctuation is produced in the video signal Video1 on the video line, as indicated by a solid-line arrow. At this moment, since the preceding sampling pulse A has not yet fallen completely, the potential fluctuation (charge/discharge noise) on the video line is picked up, as indicated by a dotted-line arrow. Consequently, a potential variation sampled on the signal line is caused to appear as a vertical streak on the screen, hence deteriorating the image quality eventually. Furthermore, because of such interference of the video signal between the signal lines connected to the same video line, there may occur a ghost or the like on the screen.